1. Field of the Invention
The invention relates to a fabrication method of forming a gate and a structure of a gate. More particularly, this invention relates to a method for increasing the effective surface area of the dielectric layer between the gates (a dielectric layer between a floating gate and a control gate).
2. Description of the Related Art
Stacked-gate non-volatile memory devices such as erasable programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM) and flash memory, have attracted great attention and research due to excellent data storage properties without applying additional electric field.
The current-voltage (I-V) characteristics of the stacked-gate non-volatile memory devices can be derived from the I-V characteristics and the coupling effect of the conventional metal-oxide semiconductor (MOS) device. Usually, the higher the capacitive coupling effect a device has, the lower operation voltage is required.
FIG. 1 shows a structure of a conventional stacked-gate non-volatile flash memory after forming and patterning conductive layers 26 and 50. The conductive layers 26 and 50 construct a floating gate. A dielectric layer 24 is formed as the gate dielectric layer between the substrate and the floating gate. In FIG. 1B, a dielectric layer 52 is formed on the floating gate, and a control gate is formed on the dielectric layer 52. The control gate includes a conductive layer 54. Both FIGS. 1A and 1B have a gate 58 and a non-gate region 60. The conductive layers 26 and 50 in the non-gate region 60 are removed while patterning the dielectric layer 52 and the conductive layer 54.
FIG. 2 shows a cross-sectional view of FIG. 1 taken along the line II--II. In FIG. 2, a gate is formed on a substrate comprising a semiconductor substrate 20, a source region 22 and a drain region 23. The gate comprises the gate dielectric layer 24, the conductive layers 26 and 50, the dielectric layer 52 and the conductive layer 54. The conductive layer at least includes one layer. The gate dielectric layer 24 is a dielectric layer between the gate and the substrate. Conductive layers 26 and 50 together form a floating gate. The dielectric layer 52 is a dielectric layer between gates. The conductive layer 54 is a control gate.
The conventional stacked-gate non-volatile flash memory comprises four junction capacitors. They are C.sub.FG between the floating gate (the conductive layers 26 and 50) and the control gate (the conductive layer 54), C.sub.B between the floating gate and substrate 20, C.sub.S between the floating gate and the source region 22, and C.sub.D between the floating gate and the drain region 23.
The capacitive coupling ratio can be represented by: ##EQU1##
According to the above equation, when the junction capacitor C.sub.FG increases, the capacitive coupling ratio increases.
The method for increasing the junction capacitance C.sub.FG includes increasing the effective surface of the dielectric layer between gates (the floating gate and the control gate), reducing the thickness of the dielectric layer between gates, and increasing the dielectric constant (k) of the dielectric layer between gates.
The dielectric layer between the floating gate and the control gate requires a sufficient thickness to prevent the electrons within the floating gate from flowing into the control gate during operation, resulting in device failure.
The increase of the dielectric constant of the dielectric layer between the floating gate and the control gate involves the replacement of fabrication equipment and the maturity of fabrication technique. Thus, it is not easy to increase the dielectric constant.
Therefore, increasing the effective surface area of the dielectric layer between the floating gate and the control gate becomes a trend for increasing the capacitive coupling ratio.
Referring to FIGS. 1A, 1B and 2, when the dielectric layer 52 and the conductive layer 54 are patterned, the conductive layer 54, the dielectric layer 52, the conductive layers 50 and 26 in the non-gate region are removed. Since the conductive layer 50 has a thickness, the vertical etching thickness of the dielectric layer 52 is greater than the lateral etching thickness of the dielectric layer 52. Thus, it causes difficulty in etching. The dielectric layer residue of the dielectric layer 52 is even left.
The signal storage of the dynamic random access memory (DRAM) is performed by selectively charging or discharging the capacitors on the surface of a semiconductor substrate. The reading or writing operation is executed by injecting or ejecting charges from the storage capacitor connected to a transfer field effective transistor and bit lines.
The capacitor is thus the heart of a dynamic random access memory. When the surface of the memory cell is reduced, the capacitance is reduced. As a consequence, the read-out performance is dearaded, the occurrence of soft errors is increased, and the power consumption during low voltage operation is increased. Increasing the surface area of the dielectric layer between the bottom and top electrode becomes one effective method to resolve the above problems.
FIG. 3 is a schematic, cross-sectional view of a conventional stacked gate. A device structure 82 is formed on the semiconductor substrate 80. A dielectric layer 84 is formed over the semiconductor substrate 80. An opening 86 is formed in the dielectric layer 84 to expose the device structure 82. A bottom electrode connected to a conventional stacked transistor is formed to fill the opening 86 and cover a portion of the dielectric layer 84. Since the bottom electrode 88 is a stacked type, the surface of the bottom electrode 88 is limited by its shape. The bottom electrode 88 for the conventional stacked-type transistor is not great.
Cylinder capacitors have increased surface areas. However, many photomasks are required in the fabrication process. The fabrication is complex and time-consuming.